This article is from the history of electronics series: Chronicles of Graphics Chips.
Reality Simulation Systems (RSSI) founded in 1993 at Venture Creations of Rensselaer Polytechnic Institute, RPI’s incubator in Troy, New York, through Mike Lewis and Steve Morein. The purpose of expanding a cost-effective and high-performance 3D graphics processor for the interactive electronic entertainment market.
The company has developed a mosaic design called PixelSquirt. More in the main designer of the company’s first chip and fostered by Microsoft’s Talisman project and VideoLogic’s PowerVR.
In 1994, Lewis and Morein moved to San Jose to be closer to the action in Silicon Valley. Lewis attracted the interest of angel investors and, in 1995, was able to raise additional capital to improve the design.
Lewis and Morein said PixelSquirt’s 3D architecture brings several innovations over classic methods of 3D rendering. superior solution established through IBM in 1987 with the 8514/A.
In 1996, S-MOS Systems and CISO announced a long-term development and commercialization agreement to design 3D generation and for private computers. S-MOS worked with Steve Morein to expand the SPC1515 PIX.
Morein said at the time: “Even with falling memory costs, reinventing 2D values it. Instead, make [the PIX] work with any board that supports DirectDraw surfaces. When asked if the engineering team would gain advantages from Tseng’s IMA port, Morein commented that they were reading this method.
When asked about the competitors, Sandeep Gupta of S-MOS said, “The performance, maybe, but the real festival is a pair of skates as a Christmas gift. “
RSSI moved away from search and write returns to the processor and instead used 250 KB of on-chip cache. It has also developed a special-purpose code that can take credit for the Pentium’s dual pipeline, similar to a classic symbol generator. said that the next edition of the chip will take advantage of AGP (Accelerated Graphics Port).
SCP1515 performed texel address calculations with spot sampling for texture mapping and compatible solution cards from 32 × 32 to 1024 × 1024. Textures were stored in host system memory and the chip processed 65,536 separate texture cards and up to 128 MB of texture supported. map data. PIX also supported PCI burst transfers.
When asked about comparisons to Talisman’s transmission processor concept, Morein said, “We have the mosaic and we reject it. They do a smart job, but it’s better if you don’t have to use them. We perform a texture search after visibility. Rendered in the texture maps and then looked for the texture of the software.
Morein said it could experience motion speeds in excess of 100 MB/s over PCI, but would not work with VGA chips that insert “unprepared” commands. × 480). At 800×600, the chip reaches forty-five megapixels/s.
Under the terms of the agreement, S-MOS would source production through its subsidiary, Seiko Epson in Japan, while also providing sales, marketing and joint development resources around the world. The CISO would gain key generation and design expertise at all stages of development. association a break and validation for CISO.
Seiko (and still is) a highly reputable precision generation company, and the Japanese are very diligent in their partnerships. The last thing the 115-year-old company wanted was to embarrass or tarnish its reputation.
Tom Endicott, vice president of marketing and sales at S-MOS, said, “We chose to work with RSSI because of their unique, cutting-edge technology for three-dimensional design for private computers and their express knowledge of the computer gaming market. “While others overcame the challenge of 3D graphics from a workstation, Array’s CISO overcame the PC user challenge.
The first chip of the 3 planned to exit the deal was the SPC1515 or PIX (PixelSquirt). S-MOS has announced that it targets video games and VRML 3-d. Lewis said S-MOS will use the buffer and main memory. of the existing 2D graphics subsystem to reduce costs and performance. When S-MOS planned the bill of materials, it said it would charge $60 for a 3D upgrade card with the PIX. This was a competitive value for the market segment the company was targeting. . But it turned out that this was not feasible.
S-MOS presented the graphics chip concept at the 1996 Computer Game Developers Conference. The positive of the company about the upcoming announcement of a victory in the design of motherboards. But it never went into production.
The PixelSquirt without an RSSI symbol buffer debuted at the CGDC in 1995. At the conference, CISO President David Bernstein said, “Our dating with S-MOS has created an ongoing partnership to enable the full progression and advent of our flexible 3-D graphics technology. The simplicity of RSSI designs combined with the first-class production conveniences of S-MOS will enable very fast product cycles, as required by the PC market.
RSSI has developed a scalable symbol generator. High-performance simulation and visualization systems, such as flight simulators, use symbol generators. For higher performance, it was imaginable to chain several PixelSquirts.
The company built an expansion card (AIB) with 4 PixelSquirts and a main controller. The AIB accepted a video stream from a VGA card through the server as a connector and then shaded the polygons. Extracted the data from the edge of the PCI bus polygon. It returned 100,000 flat triangles of 400 pixels/s, with a fill ratio greater than 3 Gpixel/s.
The AIB can provide only 2000 triangles consistent with the frame, regardless of frame rate. The AIB featured a 24-bit color with a 1-bit alpha aircraft and a 24-bit Z buffer. The chip supported resolutions up to 1024 × 768.
RSSI introduced the 4 PixelSquirts, with a DAC and a master controller chip in an AIB they called LittleSquirt, with an estimated value of less than $500. Although the AIB is not suitable for the budgets of the players, the design showed the functions of the company and the value was less expensive than the popular symbol generators. But, even with the S-MOS, military and advertising aircraft corporations hesitated to work with such a small company. As has been proven time and time again, large corporations like to deal with giant corporations.
In mid-1997, the company began work on a new architecture, Aquila PX, and scoffed at an announcement for March 1998.
Aquila PX featured video and 2D TV output, high-performance 3D and simultaneous NTSC/PAL. Lewis said the design would provide a hundred megapixels/s. It had a floating point configuration engine, 4K texture cache, 230MHz LUT-DAC. and a three-line nonlinear flicker for TV output. Lewis said Aquila PX supports a resolution of 1024 × 768 × 16 with a 1 MB texture buffer in a 4 MB configuration.
A tracking chip, the VelaTX, a 3D-only processor that Lewis says could be successful at 250 megapixels/s, and incorporated many complex 3D features, such as anisotropic textures. VelaTX would work with any existing 2D graphics accelerator, Lewis said. The three-dimensional cores of any of the devices were available for licensing.
In 1997, Morein left ciso and joined AMD. Aquila PX never left the lab. But in 1998, the company announced its VelaTX.
In late 1997, RSSI restructured and renamed Stellar Semiconductor. With the help of Sky Capital, Stellar purchased RSSI’s assets, which included the design of a new three-dimensional chip called Aquila PX. Some executives left S-MOS Systems to help identify the company, adding Sandeep Gupta. Gupta had been a senior graphics product manager at S-MOS and became the CEO of Stellar. Joseph C. Del Rio, vice president of engineering and co-founder of Stellar, executive director of engineering at S-MOS. And Michael Lewis, the company’s CTO, at RSSI before moving on to Stellar.
The company was presented at the 1998 Electronic Intellectual Property Seminar (IP98) in Santa Clara, California. At the time, the company had more than 25 workers and completed two rounds of threat funding. At that time, S-MOS was going its own way.
Due to pending patent applications, there were few main points at the time. Gupta said the design would achieve maximum performance, the best solution and the realism of the best quality. In addition, the architecture (such as Talisman and PowerVR) did not use a Z buffer and presented a real-time flow of knowledge while being part of the doors of the solutions of choice. The architecture evolved in 1993 and was implemented in an AIB a year later.
Stellar planned to expand the intellectual assets (IP) of a 3D graphics engine. “We also plan to enter the factoryless semiconductor business through the creation, market placement and promotion of graphics engines for the expansion card box and desktop motherboards,” Gupta said. However, Gupta added that the Stellar graphics accelerator would target a niche market in three-dimensional space, a market underserved by graphics companies.
Stellar had two licensees registered for its 3D core, but declined to comment on who they were. Broadcom maximum maximum is probably one of them.
The company planned to introduce a proprietary three-dimensional graphics engine in the current quarter of 1998 as a synthesized HDL network list, and claimed to have two qualified foundries to build it.
The first 3D core was compatible with DirectX 5. 0 and the company said it would use less than 250,000 doors and be synthesizable up to 100 MHz. Stellar claimed to have shown the silicon core twice with Direct3-d and OpenGL software drivers. Gupta said stellar would take less than a week to attach the existing 3D base design to a company’s device. “Because the architecture is channeled, a company can balance the functionality load and host interface well,” he added.
The 3-d IP core and graphics chips used RSSI’s original PixelSquirt architecture based on a parallel processor and multi-pipeline design. PixelSquirt’s mosaic engine eliminated Z buffering by removing hidden surfaces before filtering, texture mapping, and atmospheric conditioning. .
Stellar described VelaTX as the first of a group of 3D rendering engines based on the PixelSquirt architecture. The company claimed it would generate 200 Mpixel/s without Z buffering. Removing the Z buffer, Stellar said, reduces the requirement. for fast memory. Previously, PixelSquirt was presented as a synthesizable core.
Instead of rendering one polygon at a time, PixelSquirt rendered one pixel at a time in frame order, starting with the 24-bit floating-point hidden surface. The remaining operations only act on the output of knowledge on the screen.
The chip had 2. 5 MB of DRAM built into the rendering engine via a 512-bit bus to speed up texture mapping. The additional texture garage used external SDRAM up to 8 MB. Stellar said VelaTX will have many Open GL and DirectX 6 features on the hardware, adding attitude correction, specular highlighting, alpha combination and texture combination modes, multiple fog modes, and texture compression.
The design featured an AGP to PCI bridge, P-Pipe, VIP/VMI ports, and a memory expansion bus, allowing the chip to form a hub for multimedia expansion AIBs. VelaTX packaged in a 388-pin BGA and priced at $35 each in quantities of 10,000. Stellar said it would be available in the fourth quarter of 1998 or the first quarter of 1999.
At the 1999 Seminar on Intellectual Property in Electronics (ip99), Stellar and Sican GmbH (Hannover, Germany) announced a marketing and sales agreement. Sican agreed to market and sell Stellar’s IP cores along with Sican’s existing core product library. offering design to Stellar’s clientele.
According to Valentin von Tils, Sican’s vice president of design, the two companies’ core IP offerings would complement others. Sican featured audio and video decoding, broadband media access, and bus interface cores. The addition of graphics to the package has given Sican a larger footprint in the multimedia, communication and network application segments.
von Tils added: “Our combined strength will particularly be Sican’s ability to supply a physically powerful core set for consumers designing system-on-a-chip multimedia responses in Europe. The deal seemed like a smart fit, but it would be short-lived. .
After several months of negotiations, Broadcom announced it would get Stellar Semiconductor for the high-speed communication chipmaker entering the decoder (STB) and portable Internet device markets. “This acquisition provides Broadcom with a vital piece of generation needed to deliver high-end three-dimensional games to virtual set-top boxes,” said Broadcom CEO Henry Nicholas.
“After working with Broadcom for nearly a year, we are excited to join forces to meet the developing customer virtual entertainment market,” said Gupta.
Broadcom said it would account for the acquisition as a combination of interest. A one-time rate in the first quarter would apply to transaction-like expenses.
Broadcom tried to use the Stellar generation on an STB chip, but struggled to find many OEMs willing to pay the price for improved performance. In addition, cable companies did not have the content, nor the bandwidth, to make intelligent use of the Stellar generation over time. Lewis left Broadcom a few years later and, in 2015, introduced Mycroft AI, an open source Amazon Echo and Google Home.
Read more articles in the electronics series: Graphics Chip Chronicles.