It turns out that Micron this morning spilled the beans on the long-term of graphics card reminiscence technologies and released one of NVIDIA’s next-generation RTX video cards in the process. In a technical note published on its website, called “The Demand for Ultra Bandwidth Solutions,” Micron detailed its portfolio of broadband memory technologies and market needs. This folder contained data about gdDR6X memory technology unpublished in the past, as well as data about what appears to be the first card to use, NVIDIA’s GeForce RTX 3090.
The document appears to have been released a month (or more) earlier, given the mention of the NVIDIA card, which we do not expect to be announced before the NVIDIA event in September. In addition, the document refers to other as yet unpublished Micron technical notes involving GDDR6X. However, the document comes directly from Micron’s public Internet servers, so today we have an unexpected view of Micron’s upcoming GDDR memory plans.
However, as this is a market review that is a thorough technical immersion, the main points on GDDR6X are scarce. The article refers to another unpublished document, “Duplicate I/O functionality with PAM4: Micron innovates GDDR6X to speed up graphics memory”, which would probably involve more main points about GDDR6X. However, even this high-level review gives us a fundamental concept of what Micron has in store for the end of this year.
The key innovation for GDDR6X turns out to be that Micron is moving from NRZ encoding on the reminiscence bus, a form of binary encoding (two states), to the four-state encoding in the form of pulse amplitude modulation four (PAMfour). In short, Micron would double the number of signal states on the GDDR6X memory bus, which is consistent with allowing it to transmit twice as much clock-consistent knowledge.
PAM4 itself is a new generation and has been used in other high-end devices such as network transmitters-receivers much earlier. More recently, ICH-SIG announced that it would adopt PAM4 encoding for PCIe 6.0. So, for a little more detailed discussion about PAM4, here’s our explanation of our PCIe 6.0 manual:
At a very high level, what PAMfour does compared to NRZ (binary encoding) is to take a page from the MLC NAND playbook and double the number of electrical states that a single mobile will contain (or in this case, the transmission). Instead of the top/low classic signature, PAMfour uses four signal levels, so a signal can encode four imaginable two-bit models: 00/01/10/11. This allows PAMfour to provide twice as much knowledge as NRZ without having to double the transmission bandwidth, which for PCIe 6.0 would have resulted in a frequency of about 30 GHz (!).
PAM4 itself is not a new technology, however, until now it was the domain of ultra-high-end network criteria such as Ethernet 200G, where the amount of area available for more physical channels is even more limited. As a result, the industry already has a few years of delight running on the signaling standard, and with its own bandwidth needs proceeding to grow, the ICH-SIG introduces it internally into the chassis based on the next generation of PCIe on it. Training
The compensation to use PAM4 is, of course, the cost. Even with its higher bandwidth via Hz, PAM4 lastly costs more to put into effect at almost every level, from PHY to the physical layer. That’s why it hasn’t taken the global through the typhoon and why NRZ continues to be used elsewhere. PCIe’s massive implementation scale, of course, will help a lot here (economies of scale still count a lot), however, it will be attractive to see where things will be in a few years, once PCIe 6.0 is booming.
Until now, PAM4 signaling has only been used for network and extension buses, so using it for a reminiscences bus, a logical extension, would be a great technological leap. Now, Micron wants to expand a reminiscence that can not only leave the PAM4 modulation blank, which is not an undeniable task, but NVIDIA wants a reminiscence driver that matches the other end. It is feasible, and probably inevitable, however, it is a major replacement for the way reminiscencent buses operated historically, even high-speed buses like those used for GDDR.
According to Micron’s report, they expect to get GDDR6X at 21 Gbps/pin, at least to get started. This is far from doubling the existing flow of 16 Gbps/PIN of GDDR6, but it is also a knowledge flow that would be anchored within the limits of PAM4 and DRAM. PAM4 itself is less complicated to get binary encoding into the same general knowledge flow, however, having to figure out 4 states instead of two is a more complicated task. A smaller jump is not too surprising.
Meanwhile, it leaves the main frequency of DRAM as a persistent problem. As a reminder, the functionality of DRAM cells has stagnated more or less years ago (you can only control a combined transistor/condenser device temporarily), so new memory technologies have been an ever-increasing parallel. For GDDR technologies, for example, this means that the GDDR6 16Gbps has the same central clock frequency as the GDDR5 8Gbps. Therefore, to succeed at a knowledge rate of 21 Gbps, it is not transparent if Micron increases the clock speed of the main DRAM or if it divides it and is based on greater parallelism (for example, a larger pre-retirement size). Given what the next-generation GDDR5 memory was able to do, I guess Micron is just boosting the center clock speed for GDDR6X, but it will be attractive to see what they do.
The other big prankster right now will be the charges. As I mentioned earlier, PAM4 has been in existence for some time; Its use is expensive due to the engineering and silicon required. How much will it cost to load PAM4 on a memory chip? Obviously, this is a high-end reminiscent technology, while there is a smart chance that Micron won’t go down this path if it charges as much as HBM, which has already become prohibitive for conventional videos. Letters
Then there is one last nugget of attractive data about GDDR6X in Micron’s white package, namely power consumption. One of the indirect benefits of PAM4 is that when running a bus at a lower clock frequency than would be required in a different way, power consumption needs decrease. This is by no means a double difference, as the complexity of PAM4 encoding consumes energy in other ways, but is nevertheless more efficient. And according to Micron, this will also apply to GDDR6X, as GDDR6X has a slightly lower power load according to the bit.
According to Micron’s memory, we are looking for an average device strength of approximately 7.25 peak peaks consistent with performance for GDDR6X, compared to 7.5 for GDDR6. According to this data, the power of strength is also relatively close to HBM2, albeit hbM2E. That said, because the power is consistent with the throughte, it means that the actual strength intake depends on the bandwidth; and although GDDR6X is a little more efficient, it deserves to be much faster. Therefore, according to Micron data, the total electricity intake of GDDR6X will be higher than that of GDDR6, approximately 25%.
In general, Micron presents PAM4 as the herbal evolution of GDDR reminiscence technology. And while this is involved in apparent technical marketing, there is a real nugget, as official knowledge flows for GDDR6 still exceed 16 Gbps. Rambus, for its part, has demonstrated a GDDR6 of 18 Gbps in laboratories, but from the outside it is not transparent at this time if this is commercially viable – no reminiscence provider lately has 18 Gbps chips in its catalog.
But whatever the end point of the GDDR6 vanilla, the reminiscence industry as a total has long been regarded as the speed of reminiscence buses. Successive inhabitants have used various techniques to improve knowledge rates, such as GDDR6 QDR, however, GDDR has remained a popular asymmetric I/O that employs binary coding. With pin movement speeds now higher than 16 GT/second, one of those two basic principles will eventually have to change, as we have noticed in other spaces using high-speed I/O.
PAM4, in turn, is probably the maximum to be the least of two evils. Discarding binary encoding for PAM4 is at least the option of maximum energy efficiency. The other solution would have been to eliminate asymmetric I/O for differential signaling, which the reminiscence industry would like. Differential matrix signaling works, and works well; GDDR6 even uses it for synchronization (not reminiscences transfers), but it consumes a lot of pins and even more power. That’s a component of explaining why HBM came. Therefore, in a sense, PAM4 can be noticed as another form of differential signaling in GDDR for at least some other generation.
Finally, as we communicate about the inhabitants of reminiscence, it is worth mentioning the apparent absence of JEDEC in Micron’s article. The advertising organization and the popular configuration framework are guilty of defining the popular GDDR reminiscence, adding GDDR6, as well as Micron’s past attempt to derive reminiscent technology, GDDR5X. Given the untimely nature of the archive publication, it is not transparent if GDDR6X is some other popular JEDEC that is lately in personal progression before a public release, or if Micron goes alone and has evolved its own popular reminiscence.
Finally, let’s tell the secret of the moment into Micron’s summary, NVIDIA’s GeForce RTX 3090.
In short, according to Micron, the video card will come with 12 GB of GDDR6X in a 384-bit memory bus configuration. This reminiscence, in turn, will be timed between 19 Gbps and 21 Gbps, which, at the most sensitive end of this range, would give the map 1008GB/s of reminiscence bandwidth, just below a true 1TB/s (1024GB/s) bandwidth.
Compared to NVIDIA’s current generation of GeForce cards, this would be a significant accumulation in memory bandwidth. At a minimum, we are looking for 36% more bandwidth than a GeForce RTX 2080 Ti, and at the top end of this estimate, this figure becomes a 50% jump in bandwidth. It’s still well below what NVIDIA’s Ampere-based A100 accelerator (1.6TB/s) can do, but it would be great for a map with a GDDR-type reminiscent on a 384-bit bus. And clearly this would mean a lot to feed the beast, which is a high-quality video card of the next generation.
Anyway, this is obviously far from being the last word for NVIDIA’s GDDR6X or RTX 3090, so we’ll have more to look ahead in the run-up to NVIDIA’s September event.
Header Symbol Credit: Micron, Bare DRAM Matrix (DDR5)